Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Advanced verification techniques based on learning
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Tight integration of combinational verification methods
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Novel verification framework combining structural and OBDD methods in a synthesis environment
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
An effective and efficient ATPG-based combinational equivalence checker
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Integrating CNF and BDD based SAT solvers
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
GridSAT: a system for solving satisfiability problems using a computational grid
Parallel Computing - Optimization on grids - Optimization for grids
Novel probabilistic combinational equivalence checking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel formal verification approach for RTL hardware IP cores
Computer Standards & Interfaces
FPGA based accelerator for 3-SAT conflict analysis in SAT solvers
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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