Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Functional approaches to generating orderings for efficient symbolic representations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Heuristic minimization of BDDs using don't cares
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Probabilistic construction and manipulation of free Boolean diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Logic Synthesis of 100-percent Testable Logic Networks
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Error correction based on verification techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
An efficient assertion checker for combinational properties
DAC '97 Proceedings of the 34th annual Design Automation Conference
An efficient filter-based approach for combinational verification
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Combinational equivalence checking using satisfiability and recursive learning
DATE '99 Proceedings of the conference on Design, automation and test in Europe
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Combinational equivalence checking using Boolean satisfiability and binary decision diagrams
Proceedings of the conference on Design, automation and test in Europe
Automatic partitioning for efficient combinatorial verification
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
A practical and efficient method for compare-point matching
Proceedings of the 39th annual Design Automation Conference
Combinational and sequential equivalence checking
Logic Synthesis and Verification
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table
Formal Methods in System Design
Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Incremental logic rectification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Efficient equivalence checking with partitions and hierarchical cut-points
Proceedings of the 41st annual Design Automation Conference
An effective and efficient ATPG-based combinational equivalence checker
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Kauffman networks: analysis and applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On analysis and synthesis of (n, k)-non-linear feedback shift registers
Proceedings of the conference on Design, automation and test in Europe
A Computational Scheme Based on Random Boolean Networks
Transactions on Computational Systems Biology X
A BDD-based verification method for large synthesized circuits
Integration, the VLSI Journal
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