Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Advanced verification techniques based on learning
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Regular layout generation of logically optimized datapaths
Proceedings of the 1997 international symposium on Physical design
Novel verification framework combining structural and OBDD methods in a synthesis environment
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Logic Synthesis of 100-percent Testable Logic Networks
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Benchmark-Circuits for Hardware-Verification
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
Exploiting Structural Similarities in a BDD-Based Verification Method
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
VERIFUL: VERIfication using FUnctional Learning
EDTC '95 Proceedings of the 1995 European conference on Design and Test
DAC '81 Proceedings of the 18th Design Automation Conference
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Nowadays, logic synthesis tools are widely used to optimize and implement digital systems. Verifying the correctness of the generated circuits is an important practical problem. We present a new formal verification method for large synthesized circuits. It combines the use of binary decision diagrams (BDDs) with techniques to exploit the structural similarities of the circuits under comparison. These similarities are detected automatically. We show that the proposed method significantly extends the capability of BDD-based methods to verify large synthesized circuits.