On diagnosis and correction of design errors
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Incremental logic synthesis through gate logic structure identification
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Incremental Synthesis for Engineering Changes
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Error correction based on verification techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Regular layout generation of logically optimized datapaths
Proceedings of the 1997 international symposium on Physical design
Engineering change: methodology and applications to behavioral and system synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Efficient error detection, localization, and correction for FPGA-based debugging
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Design Error Diagnosis with Re-Synthesis in Combinational Circuits
Journal of Electronic Testing: Theory and Applications
Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Incremental logic rectification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
ErrorTracer: A Fault Simulation-Based Approach to Design Erorr Diagnosis
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Efficient Design Error Correction of Digital Circuits
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Technique for Identifying RTL and Gate-Level Correspondences
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Design and design automation of rectification logic for engineering change
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Incremental component implementation selection: enabling ECO in compositional system synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Engineering change using spare cells with constant insertion
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Accurate rank ordering of error candidates for efficient HDL design debugging
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Spare cells with constant insertion for engineering change
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A formal approach for debugging arithmetic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DeltaSyn: an efficient logic difference optimizer for ECO synthesis
Proceedings of the 2009 International Conference on Computer-Aided Design
A BDD-based verification method for large synthesized circuits
Integration, the VLSI Journal
Incremental high-level synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Line-level incremental resynthesis techniques for FPGAs
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Interpolation-based incremental ECO synthesis for multi-error logic rectification
Proceedings of the 48th Design Automation Conference
Intuitive ECO synthesis for high performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Partial synthesis through sampling with and without specification
Proceedings of the International Conference on Computer-Aided Design
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A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only.