Rectification method for lookup-table type FPGA's
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ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
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FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
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FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
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FPGA logic density is roughly doubling at every process generation. Consequently, it is becoming increasingly challenging for FPGA CAD tools to keep up with the growing complexities of high-speed designs while keeping CAD run-times reasonable. In this paper, we present a novel incremental resynthesis tool called Line-Level Incremental reSynthesis (LLIS), integrated within an industrial tool suite, that addresses the problems of timing closure as well as CAD runtime (patent pending). We describe a general framework that can incrementally reuse results from a previous compile based on automatic differencing of HDL changes. We show that it is possible to reduce synthesis runtime by 6.5x for common HDL changes. As compared with complete resynthesis, we preserve known good timing solutions more than 82% of the time. This represents a 3X improvement vs. non-incremental techniques.