Line-level incremental resynthesis techniques for FPGAs
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Scalable and deterministic timing-driven parallel placement for FPGAs
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
GPU programming for EDA with OpenCL
Proceedings of the International Conference on Computer-Aided Design
Distributed simulated annealing with mapreduce
EvoApplications'12 Proceedings of the 2012t European conference on Applications of Evolutionary Computation
A simulated annealing algorithm for GPU clusters
PPAM'11 Proceedings of the 9th international conference on Parallel Processing and Applied Mathematics - Volume Part I
Journal of Parallel and Distributed Computing
Parallel neighbourhood search on many-core platforms
International Journal of Computational Science and Engineering
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Simulated annealing has became the de facto standard for FPGA placement engines since it provides high quality solutions and is robust under a wide range of objective functions. However, this method will soon become prohibitive due to its sequential nature and since the performance of single-core processor has stagnated. General purpose computing on graphics processing units (GPGPU) offers a promising solution to improve runtime with only commodity hardware. In this work, we develop a highly parallel approach to simulated annealing-based placement using GPGPU. We identify the challenges posed by the GPU architecture and describe effective solutions. An average speedup of about 10x was achieved over conventional placement within 3% of wirelength.