Introduction to algorithms
Field-programmable gate arrays
Field-programmable gate arrays
Plane parallel a maze router and its application to FPGAs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Transmogrifier-2: a 1 million gate rapid prototyping system
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Generation of synthetic sequential benchmark circuits
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
The RAW benchmark suite: computation structures for general purpose computing
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
DAC '78 Proceedings of the 15th Design Automation Conference
A topologically adaptable cellular router
DAC '76 Proceedings of the 13th Design Automation Conference
Architectures and algorithms for field-programmable gate arrays with embedded memory
Architectures and algorithms for field-programmable gate arrays with embedded memory
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Fast compilation for pipelined reconfigurable fabrics
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
New parallelization and convergence results for NC: a negotiation-based FPGA router
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Tolerating operational faults in cluster-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
LRoute: a delay minimal router for hierarchical CPLDs
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A comparative study of two Boolean formulations of FPGA detailed routing constraints
Proceedings of the 2001 international symposium on Physical design
Timing-driven routing for FPGAs based on Lagrangian relaxation
Proceedings of the 2002 international symposium on Physical design
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Fast placement approaches for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Stochastic, spatial routing for hypergraphs, trees, and meshes
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
JRoute: A Run-Time Routing API for FPGA Hardware
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Placement/Routing Approach for FPGA Accelerators
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Efficient Place and Route for Pipeline Reconfigurable Architectures
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Min-Cost Flow Based Detailed Router for FPGAs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On metrics for comparing interconnect estimation methods for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Congestion estimation and localization in fpgas:: a visual tool for interconnect prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Modeling routing demand for early-stage FPGA architecture development
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Line-level incremental resynthesis techniques for FPGAs
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Choose-your-own-adventure routing: Lightweight load-time defect avoidance
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Networked architecture for hybrid electrical energy storage systems
Proceedings of the 49th Annual Design Automation Conference
Run-time generation of partial FPGA configurations for subword operations
Microprocessors & Microsystems
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Hi-index | 0.00 |
Three factors are driving the demand for rapid FPGA compilation. First, as FPGAs have grown in logic capacity, the compile computation has grown more quickly than the compute power of the available computers. Second, there exists a subset of users who are willing to pay for very high speed compile with a decrease in quality of result, and accordingly being required to use a larger FPGA or use more real-estate on a given FPGA than is otherwise necessary. Third, very high speed compile has been a long-standing desire of those using FPGA-based custom computing machines, as they want compile times at least closer to those of regular computers.This paper focuses on the routing phase of the compile process, and in particular on routability-driven routing (as opposed to timing-driven routing). We present a routing algorithm and routing tool that has three unique capabilities relating to very high-speed compile:For a “low stress” routing problem (which we define as the case where the track supply is at least 10% greater than the minimun number of tracks per channel actually needed to route a circuit) the routing time is very fast. For example, the routing phase (after the netlist is parsed and the routing graph is constructed) for a 20,000 LUT/FF pair circuit with 30% extra tracks is only 23 seconds on a 300 MHz Sparcstation.For low-stress routing problems the routing time is near-linear in the size of the circuit, and the linearity constant is very small: 1.1 ms per LUT/FF pair, or roughly 55,000 LUT/FF pairs per minute. For more difficult routing problems (where the track supply is close to the minimum needed) we provide a method that quickly identifies and subdivides this class into two sub-classes: (i) those circuits which are difficult (but possible) to route and will take significantly more time than low-stress problems, and (ii) those circuits which are impossible to route. In the first case the user can choose to continue or reduce the amount of logic; in the second case the user is forced to reduce the amount of logic or obtain a larger FPGA.