Data structures and network algorithms
Data structures and network algorithms
A method for generating random circuits and its application to routability measurement
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Characterization and parameterized random generation of digital circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Directional bias and non-uniformity in FPGA global routing architectures
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A Technique for Drawing Directed Graphs
IEEE Transactions on Software Engineering
A fast routability-driven router for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Generation of very large circuits to benchmark the partitioning of FPGA
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Tolerating operational faults in cluster-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Benchmarking in digital circuit design
MINO'08 Proceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics
Benchmarking in digital circuit design automation
WSEAS Transactions on Circuits and Systems
Progress in autonomous fault recovery of field programmable gate arrays
ACM Computing Surveys (CSUR)
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Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the effectiveness of new architectures and software. Benchmark circuits arc a precious commodity, and often cannot be found at the correct granularity, or in the desired quantity. In previous work, we have defined important physical characteristics of combinational circuits. We presented a tool (CIRC) to extract them, and gaue an algorithm and tool (GEN) which generates random circuits, parameterized by those characteristics or by a realistic set of defaults. Though a promising step, only a small portion of real circuits are fully combinational. In this paper we extend the effort to model sequential circuits. We propose new characteristics and generate circuits which are sequential. This allows for the generation of truly useful benchmark circuits, both at and beyond the sizes of next-generation FPGAs. By comparing the post-lay out properties of the generated circuits with already existing circuits, we demonstrate that the synthetic circuits are much more realistic than random graphs with the same number of nodes, edges and I/Os.