Field-programmable gate arrays
Field-programmable gate arrays
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Generation of synthetic sequential benchmark circuits
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Proceedings of the 1997 international symposium on Physical design
More wires and fewer LUTs: a design methodology for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
An LPGA with foldable PLA-style logic blocks
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Detailed routing architectures for embedded programmable logic IP cores
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Length-Matching Routing for High-Speed Printed Circuit Boards
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An integrated design flow for a via-configurable gate array
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes
IEEE Transactions on Computers
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs
IEEE Transactions on Computers
Routing architecture optimizations for high-density embedded programmable IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A routing fabric for monolithically stacked 3D-FPGA
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A low-power field-programmable gate array routing fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance-driven dual-rail insertion for chip-level pre-fabricated design
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring FPGA routing architecture stochastically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Effect of the prefabricated routing track distribution on FPGA area-efficiency
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
On power and fault-tolerance optimization in FPGA physical synthesis
Proceedings of the International Conference on Computer-Aided Design
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This paper investigates the effect of the prefabricated routing track distribution on the area-efficiency of FPGAs. The first question we address is whether horizontal and vertical channels should contain the same number of tracks (capacity), or if there is a density advantage with a directional bias. Secondly, should the channels have a uniform capacity, or is there an advantage when capacities vary from channel to channel? The key result is that the most area-efficient global routing architecture is one with uniform (or very nearly uniform) channel capacities across the entire chip in both the horizontal and vertical directions. Several non-uniform and directionally-biased architectures, however, are fairly area-efficient provided that appropriate choices are made for the pin positions on the logic blocks and the logic array aspect ratio.