The stratixπ routing and logic architecture

Authors:
David Lewis;Vaughn Betz;David Jefferson;Andy Lee;Chris Lane;Paul Leventis;Sandy Marquardt;Cameron McClintock;Bruce Pedersen;Giles Powell;Srinivas Reddy;Chris Wysocki;Richard Cliff;Jonathan Rose
Affiliations:
Altera Toronto Technology Centre, Toronto, Ont, Canada;Altera Toronto Technology Centre, Toronto, Ont, Canada;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;Altera Toronto Technology Centre, Toronto, Ont, Canada;Altera Toronto Technology Centre, Toronto, Ont, Canada;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;Altera Toronto Technology Centre, Toronto, Ont, Canada
Venue:
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Year:
2003

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Abstract

This paper describes the Altera Stratix logic and routing architecture. The primary goals of the architecture were to achieve high performance and logic density. We give an overview of the entire device, and then focus on the logic and routing architecture. The Stratix logic architecture is based on a cluster of ten 4-input LUTs and its routing consists of staggered routing lines. We describe the development of the routing architecture, including its directional bias, its direct-drive routing which reduces both area and delay. The logic array block and logic cell design is also described, and new routing structures with in the logic array block, and logic element features are described.