The Stratix II logic and routing architecture

Authors:
David Lewis;Elias Ahmed;Gregg Baeckler;Vaughn Betz;Mark Bourgeault;David Cashman;David Galloway;Mike Hutton;Chris Lane;Andy Lee;Paul Leventis;Sandy Marquardt;Cameron McClintock;Ketan Padalia;Bruce Pedersen;Giles Powell;Boris Ratchev;Srinivas Reddy;Jay Schleicher;Kevin Stevens;Richard Yuan;Richard Cliff;Jonathan Rose
Affiliations:
Altera Corporation, Toronto, Ontario, Canada;Altera Corporation, Toronto, Ontario, Canada;Altera Corporation, San Jose, CA;Altera Corporation, Toronto, Ontario, Canada;Altera Corporation, Toronto, Ontario, Canada;Altera Corporation, Toronto, Ontario, Canada;Altera Corporation, Toronto, Ontario, Canada;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;Altera Corporation, Toronto, Ontario, Canada;Altera Corporation, Toronto, Ontario, Canada;Altera Corporation, San Jose, CA;Altera Corporation, Toronto, Ontario, Canada;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;Altera Corporation, Toronto, Ontario, Canada;Altera Corporation, San Jose, CA;Altera Corporation, San Jose, CA;University of Toronto, Toronto, Ontario, Canada
Venue:
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Year:
2005

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Abstract

This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits containing a range of LUT sizes that arises in conventional synthesis flows. This provides a performance increase of 15% in the Stratix II architecture while reducing area by 2%. The ALM also includes a more powerful arithmetic structure that can perform two bits of arithmetic per ALM, and perform a sum of up to three inputs. The routing fabric adds a new set of fast inputs to the routing multiplexers for another 3% improvement in performance, while other improvements in routing efficiency cause another 6% reduction in area. These changes in combination with other circuit and architecture changes in Stratix II contribute 27% of an overall 51% performance improvement (including architecture and process improvement). The architecture changes reduce area by 10% in the same process, and by 50% after including process migration.