Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
FPGA power reduction using configurable dual-Vdd
Proceedings of the 41st annual Design Automation Conference
The Stratix II logic and routing architecture
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
Proceedings of the 42nd annual Design Automation Conference
Low-power programmable routing circuitry for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Vdd programmability to reduce FPGA interconnect power
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction
Proceedings of the 2006 international symposium on Low power electronics and design
Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction
Proceedings of the conference on Design, automation and test in Europe
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
A high-level clustering algorithm targeting dual Vdd FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simultaneous slack budgeting and retiming for synchronous circuits optimization
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Network flow-based simultaneous retiming and slack budgeting for low power design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
SPIRE: a retiming-based physical-synthesis transformation system
Proceedings of the International Conference on Computer-Aided Design
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Field programmable dual-Vdd interconnects are effective to reduce FPGA power.Assuming uniform length interconnects,existing work has developed time slack budgeting to minimize power based on estimating the lower bound of power reduction using dual-Vdd for given time slack.In this paper,we show that such lower bound estimation cannot be extended to mixed length interconnects that are used in modern FPGAs.We develop a technique to estimate power reduction using dual-Vdd for mixed length interconnects, and apply linear programming (LP)to solve slack budgeting to minimize power for mixed length interconnects.Experiments show 53%power reduction on average compared to single-Vdd interconnects.Furthermore,this paper presents a simultaneous retiming and slack budgeting algorithm to reduce power in dual-Vdd FPGAs considering placement and.ip-.op binding constraints.The algorithm is based on mixed integer and linear programming (MILP)and achieves up to 20%power reduction compared to retiming followed by slack budgeting.We propose a runtime e fficient flow to apply simultaneous retiming and slack budgeting only when it is necessary.To the best of our knowledge,this paper is the first in-depth study of simultaneous retiming and slack budgeting for dual-Vdd programmable FPGA power reduction while considering layout constraints.