Cost minimization of partitions into multiple devices
DAC '93 Proceedings of the 30th international Design Automation Conference
Spectral-based multi-way FPGA partitioning
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Comparing algorithm for dynamic speed-setting of a low-power CPU
MobiCom '95 Proceedings of the 1st annual international conference on Mobile computing and networking
Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Low power FPGA design—a re-engineering approach
DAC '97 Proceedings of the 34th annual Design Automation Conference
Circuit partitioning for dynamically reconfigurable FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs
IEEE Transactions on Computers
Gate-level design exploiting dual supply voltages for power-driven applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low-power design methodology and applications utilizing dual supply voltages
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Power minization in LUT-based FPGA technology mapping
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Dynamic voltage scaling and power management for portable systems
Proceedings of the 38th annual Design Automation Conference
On gate level power optimization using dual-supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Some Notes on Power Management on FPGA-Based Systems
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Power efficiency of voltage scaling in multiple clock, multiple voltage cores
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Low-power high-level synthesis for FPGA architectures
Proceedings of the 2003 international symposium on Low power electronics and design
Power minimization algorithms for LUT-based FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Low-power technology mapping for FPGA architectures with dual supply voltages
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
FPGA power reduction using configurable dual-Vdd
Proceedings of the 41st annual Design Automation Conference
On the Interaction Between Power-Aware FPGA CAD Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Device and architecture co-optimization for FPGA power reduction
Proceedings of the 42nd annual Design Automation Conference
Vdd programmability to reduce FPGA interconnect power
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Proceedings of the 43rd annual Design Automation Conference
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction
Proceedings of the 2006 international symposium on Low power electronics and design
Using cone structures for circuit partitioning into FPGA packages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal integer delay-budget assignment on directed acyclic graphs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Recent advanced power optimizations deployed in commercial FPGAs, laid out a roadmap towards FPGA devices that can be integrated into ultra low power systems. In this article, we present a high-level design tool to support the process of mapping an application onto a FPGA device with dual supply voltages. Our main contribution in this paper is an algorithm, which creates voltage scaling ready clusters by utilizing the timing slack available in the designs. We propose to first create clusters of CLBs within a given CLB-level netlist. This clustering algorithm intends to group chains of CLBs possessing similar amounts of timing slack along their critical path together. Once these clusters are identified, they are placed onto respective Vdd partitions on the device. We have evaluated different dual Vdd fabrics and the potential gain in power consumption is explored. When a subset of the logic blocks on the device can be driven by low Vdd levels (either with a dedicated low Vdd supply or with a programmable selection between low and high Vdd levels for these blocks) this affects placement and routing. As a result the maximum frequency of the designs may be affected. In order to evaluate the overall impact of creating voltage islands, we measured the Energy-Delay Product for our benchmark designs. We observed that the Energy-Delay product can be decreased by 26.9% when the placement of the designs into different voltage levels is guided by our clustering algorithm.