Combinatorics for computer science
Combinatorics for computer science
Field-programmable gate arrays
Field-programmable gate arrays
Task scheduling in parallel and distributed systems
Task scheduling in parallel and distributed systems
Applications of reconfigurable logic
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
DPGA utilization and application
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Design methodologies for partially reconfigured systems
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Performance-Oriented Fully Routable Dynamic Architecture for a Field
Performance-Oriented Fully Routable Dynamic Architecture for a Field
Reconfigurable architectures for general-purpose computing
Reconfigurable architectures for general-purpose computing
Loop Pipelining and Optimization for Run Time Reconfiguration
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Implementation of Virtual Circuits by Means of the FIPSOC Devices
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Journal of Systems Architecture: the EUROMICRO Journal
A partial reconfigurable architecture for controllers based on Petri nets
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Efficient metrics and high-level synthesis for dynamically reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems
IEEE Transactions on Computers
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
Integration, the VLSI Journal
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Temporal partitioning data flow graphs for dynamically reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-level clustering algorithm targeting dual Vdd FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
A parallel partitioning algorithm for parallel reconfigurable computing
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Temporal circuit partitioning for a 90nm CMOS multi-context FPGA and its delay measurement
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A dynamic reconfigurable CPLD architecture for structured ASIC technology
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Hardware supported task scheduling on dynamically reconfigurable SoC architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power minimization for dynamically reconfigurable FPGA partitioning
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Meta-algorithms for scheduling a chain of coarse-grained tasks on an array of reconfigurable FPGAs
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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A fundamental feature of Dynamically Reconfigurable FPGAs (DRFPGAs) is that the logic and interconnect are time-multiplexed. Thus, for a circuit to be implemented on a DRFPGA, it needs to be partitioned such that each subcircuit can be executed at a different time. In this paper, the partitioning of sequential circuits for execution on a DRFPGA is studied. To determine how to correctly partition a sequential circuit and what are the costs in doing so, we propose a new gate-level model that handles time-multiplexed computation. We also introduce an enchanced force directed scheduling (FDS) algorithm to partition sequential circuits that finds a correct partition with low logic and communication costs, under the assumption that maximum performance is desired. We use our algorithm to partition seven large ISCAS '89 sequential benchmark circuits. The experimental results show that the enhanced FDS reduces communication costs by 27.5 percent with only a 1.1 percent increase in the gate cost compared to traditional FDS.