Multi-way partitioning for minimum delay for look-up table based FPGAs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Discrete-time signal processing (2nd ed.)
Discrete-time signal processing (2nd ed.)
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs
IEEE Transactions on Computers
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
MorphoSys: case study of a reconfigurable computing system targeting multimedia applications
Proceedings of the 37th Annual Design Automation Conference
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing
Journal of Systems Architecture: the EUROMICRO Journal - Modern methods and tools in digital system design
Parallel Algorithms and Architectures for DSP Applications
Parallel Algorithms and Architectures for DSP Applications
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
HW/SW codesign techniques for dynamically reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Parallel Processing Architectures for Reconfigurable Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Computer Organization and Architecture: Designing for Performance (7th Edition)
Computer Organization and Architecture: Designing for Performance (7th Edition)
Generic ILP-based approaches for time-multiplexed FPGA partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A parallel processing reconfigurable architecture consists of multiple processor elements as FPGAs. Dynamically reconfigurable computing in the architecture combines with a parallel processing technique for high-level synthesis. A new partitioning algorithm is presented based on the architecture and needs to consider parallel processing different from transitional partitioning. The algorithm minimizes execution time to maximize application performance. A program or application is represented by a directed acyclic graph. In the algorithm a graph is divided into subgraphs by applying the greedy method and obtains the minimizing depth solution. Our algorithm efficiency and effectiveness is shown in the results.