MorphoSys: case study of a reconfigurable computing system targeting multimedia applications

Authors:
Hartej Singh;Guangming Lu;Eliseu Filho;Rafael Maestre;Ming-Hau Lee;Fadi Kurdahi;Nader Bagherzadeh
Affiliations:
University of California, Irvine, Dept of Electrical & Computer Eng., Irvine, CA;University of California, Irvine, Dept of Electrical & Computer Eng., Irvine, CA;Dept of Systems and Computer Engineering, COPPE/Federal University of Rio De Janeiro, Rio de Janeiro, RJ Brazil;Dept. de Arquitectura de Comp.y Automatica, Escuela Superior de Informatica, Universidad Complutense, 28040, Madrid, Spain;University of California, Irvine, Dept of Electrical & Computer Eng., Irvine, CA;University of California, Irvine, Dept of Electrical & Computer Eng., Irvine, CA;University of California, Irvine, Dept of Electrical & Computer Eng., Irvine, CA
Venue:
Proceedings of the 37th Annual Design Automation Conference
Year:
2000

Citing 11
Cited 23

Design and implementation of the “Tiny RISC” microprocessor

Microprocessors & Microsystems
Kernel scheduling in reconfigurable computing

DATE '99 Proceedings of the conference on Design, automation and test in Europe
Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor

Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Optimal temporal partitioning and synthesis for reconfigurable architectures

Proceedings of the conference on Design, automation and test in Europe
V830R/AV: Embedded Multimedia Superscalar RISC Processor

IEEE Micro
Architectural Synthesis Techniques for Dynamically Reconfigurable Logic

FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Configurable computing: the catalyst for high-performance architectures

ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Automated target recognition on SPLASH 2

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Temporal Partitioning and Scheduling for Reconfigurable Computing

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
High-performance automatic target recognition through data-specific VLSI

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A data scheduler for multi-context reconfigurable architectures

Proceedings of the 14th international symposium on Systems synthesis
Configuration management in multi-context reconfigurable systems for simultaneous performance and power optimizations

ISSS '00 Proceedings of the 13th international symposium on System synthesis
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture

CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Continuous and high coverage self-testing of dynamically re-configurable systems

Parallel Computing - Parallel computing in image and video processing
Factors Influencing the Performance of a CPU-RFU Hybrid Architecture

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Cyclic coding algorithms under MorphoSys reconfigurable computing system

Advances in Engineering Software
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures

FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
MaRS: a macro-pipelined reconfigurable system

Proceedings of the 1st conference on Computing frontiers
Physical design methodologies for performance predictability and manufacturability

Proceedings of the 1st conference on Computing frontiers
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration

Proceedings of the 42nd annual Design Automation Conference
PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Selective bandwidth and resource management in scheduling for dynamically reconfigurable architectures

Proceedings of the 44th annual Design Automation Conference
Polymorphic On-Chip Networks

ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Integrating physical constraints in HW-SW partitioning for architectures with partial dynamic reconfiguration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
A parallel partitioning algorithm for parallel reconfigurable computing

CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
CGADL: an architecture description language for coarse-grained reconfigurable arrays

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Operation and data mapping for CGRAs with multi-bank memory

Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Exploiting application data-parallelism on dynamically reconfigurable architectures: placement and architectural considerations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory access optimization in compilation for coarse-grained reconfigurable architectures

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parallel Reconfigurable Computing-Based Mapping Algorithm for Motion Estimation in Advanced Video Coding

ACM Transactions on Embedded Computing Systems (TECS) - Special Section on CAPA'09, Special Section on WHS'09, and Special Section VCPSS' 09

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we present a case study for the design, programming and usage of a reconfigurable system-on-chip, MorphoSys, which is targeted at computation-intensive applications. This 2-million transistor design combines a reconfigurable array of cells with a RISC processor core and a high bandwidth memory interface. The system architecture, software tools including a scheduler for reconfigurable systems, and performance analysis (with impressive speedups) for target applications are described.