MaRS: a macro-pipelined reconfigurable system

Authors:
Nozar Tabrizi;Nader Bagherzadeh;Amir H. Kamalizad;Haitao Du
Affiliations:
University of California, Irvine, Irvine, CA;University of California, Irvine, Irvine, CA;University of California, Irvine, Irvine, CA;University of California, Irvine, Irvine, CA
Venue:
Proceedings of the 1st conference on Computing frontiers
Year:
2004

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Abstract

We introduce MaRS, a reconfigurable, parallel computing engine with special emphasis on scalability, lending itself to the computation-/data-intensive multimedia data processing and wireless communication. Global communication between the processing elements (PEs) in MaRS is performed through a 2D-mesh deadlock-free network, avoiding any concerns due to non-scalable bus-based communication. Additionally, we have developed a second layer of inter-PE connection realized by distributed shared register files and conditional operands, to enhance the performance of MaRS for those applications demanding a tightly coupled PE array. We have modeled and verified a major part of MaRS. The promising results of our preliminary analyses show that MaRS can efficiently be tailored to different applications offering flexible data communication, and high performance.