A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Digital Computer Arithmetic
Wideband CDMA For Third Generation Mobile Communications: Universal Personal Communications
Wideband CDMA For Third Generation Mobile Communications: Universal Personal Communications
A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Architecture Design of Reconfigurable Pipelined Datapaths
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
The NAPA Adaptive Processing Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Interconnect Architecture Exploration for Low-Energy Reconfigurable Single-Chip DSPs
WVLSI '99 Proceedings of the IEEE Computer Society Workshop on VLSI'99
Reconfigurable Processing: The Solution to Low-Power Programmable DSP
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
CELP speech coding based on an adaptive pulse position codebook
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 01
Spreading codes for direct sequence CDMA and wideband CDMA cellular networks
IEEE Communications Magazine
A Compilation Framework for a Dynamically Reconfigurable Architecture
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 3
MaRS: a macro-pipelined reconfigurable system
Proceedings of the 1st conference on Computing frontiers
Enabling certification for dynamic partial reconfiguration using a minimal flow
Proceedings of the conference on Design, automation and test in Europe
DART: a functional-level reconfigurable architecture for high energy efficiency
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Design of the coarse-grained reconfigurable architecture DART with on-line error detection
Microprocessors & Microsystems
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In addition to the high performance requirements inherent to multimedia processings or to W-CDMA, future generation mobile telecommunications brings new constraints to the semiconductor design world. In fact, to support these processings, a system will have to be very flexible, in order to support the various algorithms allowed by the norm and the addition of new services, while keeping an energy consumption level compatible with the portability notion of this system. In order to associate high performances and low energy consumption in a flexible system, we developed a dynamically reconfigurable architecture called DART. The aim of this paper is to present this architecture and to estimate its level of performance and its adequacy with future generation mobile telecommunication systems.