A flexible code generation framework for the design of application specific programmable processors
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
FPGA clock management for low power applications (poster abstract)
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Re-configurable computing in wireless
Proceedings of the 38th annual Design Automation Conference
Loop fusion for memory space optimization
Proceedings of the 14th international symposium on Systems synthesis
Wideband CDMA For Third Generation Mobile Communications: Universal Personal Communications
Wideband CDMA For Third Generation Mobile Communications: Universal Personal Communications
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
A Compilation Framework for a Dynamically Reconfigurable Architecture
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
PACT XPP—A Self-Reconfigurable Data Processing Architecture
The Journal of Supercomputing
Interconnect Architecture Exploration for Low-Energy Reconfigurable Single-Chip DSPs
WVLSI '99 Proceedings of the IEEE Computer Society Workshop on VLSI'99
Loop Alignment for Memory Accesses Optimization
Proceedings of the 12th international symposium on System synthesis
Analysis and design of low power digital multipliers
Analysis and design of low power digital multipliers
Augmenting a microprocessor with reconfigurable hardware
Augmenting a microprocessor with reconfigurable hardware
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Spreading codes for direct sequence CDMA and wideband CDMA cellular networks
IEEE Communications Magazine
PRADA: a high-performance reconfigurable parallel architecture based on the dataflow model
International Journal of High Performance Systems Architecture
Design of the coarse-grained reconfigurable architecture DART with on-line error detection
Microprocessors & Microsystems
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Flexibility becomes a major concern for the development of multimedia and mobile communication systems, as well as classical high-performance and low-energy consumption constraints. The use of general-purpose processors solves flexibility problems but fails to cope with the increasing demand for energy efficiency. This paper presents the DART architecture based on the functional-level reconfiguration paradigm which allows a significant improvement in energy efficiency. DART is built around a hierarchical interconnection network allowing high flexibility while keeping the power overhead low. To enable specific optimizations, DART supports two modes of reconfiguration. The compilation framework is built using compilation and high-level synthesis techniques. A 3G mobile communication application has been implemented as a proof of concept. The energy distribution within the architecture and the physical implementation are also discussed. Finally, the VLSI design of a 0.13 µm CMOS SoC implementing a specialized DART cluster is presented.