Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Re-configurable computing in wireless
Proceedings of the 38th annual Design Automation Conference
The Garp Architecture and C Compiler
Computer
XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A New FPGA Architecture for Word-Oriented Datapaths
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
The digital divide of computing
Proceedings of the 1st conference on Computing frontiers
Dynamic loop pipelining in data-driven architectures
Proceedings of the 2nd conference on Computing frontiers
Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices
IEEE Design & Test
A system-level approach to hardware reconfigurable systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An EDF schedulability test for periodic tasks on reconfigurable hardware devices
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units
The Journal of Supercomputing
A Simple Data Transfer Technique Using Local Address for Networks-on-Chips
IEEE Transactions on Parallel and Distributed Systems
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer
Journal of VLSI Signal Processing Systems
Enabling certification for dynamic partial reconfiguration using a minimal flow
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study
Integration, the VLSI Journal
DART: a functional-level reconfigurable architecture for high energy efficiency
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Multi-core architectures and streaming applications
Proceedings of the 2008 international workshop on System level interconnect prediction
Journal of Systems Architecture: the EUROMICRO Journal
A holistic approach for tightly coupled reconfigurable parallel processors
Microprocessors & Microsystems
IEICE - Transactions on Information and Systems
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
CGADL: an architecture description language for coarse-grained reconfigurable arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mapping of the FFT on a reconfigurable architecture targeted to SDR applications
SOC'09 Proceedings of the 11th international conference on System-on-chip
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Modeling of interconnection networks in massively parallel processor architectures
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
MORA: a new coarse-grain reconfigurable array for high throughput multimedia processing
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Customizable FPGA IP core implementation of a general-purpose genetic algorithm engine
IEEE Transactions on Evolutionary Computation
Application-specific memory performance of a heterogeneous reconfigurable architecture
Proceedings of the Conference on Design, Automation and Test in Europe
Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture
Proceedings of the Conference on Design, Automation and Test in Europe
SCMP architecture: an asymmetric multiprocessor system-on-chip for dynamic applications
Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A virtual VLSI architecture for computer hardware evolution
SAICSIT '10 Proceedings of the 2010 Annual Research Conference of the South African Institute of Computer Scientists and Information Technologists
Rapid functional modelling and simulation of coarse grained reconfigurable array architectures
Journal of Systems Architecture: the EUROMICRO Journal
Partitioning signal processing applications to different granularity reconfigurable logic
SSIP'05 Proceedings of the 5th WSEAS international conference on Signal, speech and image processing
Speedups from executing critical software segments to coarse-grain reconfigurable logic
ICCOMP'06 Proceedings of the 10th WSEAS international conference on Computers
International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
Exploring online synthesis for CGRAs with specialized operator sets
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Designing a coarse-grained reconfigurable architecture using loop self-pipelining
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems
Journal of Signal Processing Systems
Hierarchical power management for adaptive tightly-coupled processor arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
QUKU: A dual-layer reconfigurable architecture
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Implementation of FFT on General-Purpose Architectures for FPGA
International Journal of Embedded and Real-Time Communication Systems
An augmented reality system with a coarse-grained reconfigurable device
ACM SIGARCH Computer Architecture News - ACM SIGARCH Computer Architecture News/HEART '12
A high performance reliable dataflow based processor for space applications
Proceedings of the ACM International Conference on Computing Frontiers
System integration of tightly-coupled processor arrays using reconfigurable buffer structures
Proceedings of the ACM International Conference on Computing Frontiers
ACM SIGARCH Computer Architecture News
Partial online-synthesis for mixed-grained reconfigurable architectures
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Hardware evolution of a digital circuit using a custom VLSI architecture
Proceedings of the South African Institute for Computer Scientists and Information Technologists Conference
Design of the coarse-grained reconfigurable architecture DART with on-line error detection
Microprocessors & Microsystems
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The eXtreme Processing Platform (XPPTM) is a new runtime-reconfigurable data processing architecture. It is based on a hierarchical array of coarsegrain, adaptive computing elements, and a packet-oriented communication network. The strength of the XPPTM technology originates from the combination of array processing with unique, powerful run-time reconfiguration mechanisms. Parts of the array can be configured rapidly in parallel while neighboring computing elements are processing data. Reconfiguration is triggered externally or even by special event signals originating within the array, enabling self-reconfiguring designs. The XPPTM architecture is designed to support different types of parallelism: pipelining, instruction level, data flow, and task level parallelism. Therefore this technology is well suited for applications in multimedia, telecommunications, simulation, signal processing (DSP), graphics, and similar stream-based application domains. The anticipated peak performance of the first commercial device running at 150 MHz is estimated to be 57.6 GigaOps/sec, with a peak I/O bandwidth of several GByte/sec. Simulated applications achieve up to 43.5 GigaOps/sec (32-bit fixed point).