Limits of instruction-level parallelism
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Single instruction stream parallelism is greater than two
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
The El'brus-3 and MARS-M: recent advances in Russian high-performance computing
The Journal of Supercomputing
Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Computer
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
IEEE Design & Test
Linear-time connected-component labeling based on sequential local operations
Computer Vision and Image Understanding
PACT XPP—A Self-Reconfigurable Data Processing Architecture
The Journal of Supercomputing
Performance Comparison of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems
RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
Hardware implementation of a real-time operating system
TRON '95 Proceedings of the The 12th TRON Project International Symposium, 1995
RTSS '01 Proceedings of the 22nd IEEE Real-Time Systems Symposium
Hardware support for real-time operating systems
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A linear-time component-labeling algorithm using contour tracing technique
Computer Vision and Image Understanding
Chip Multithreading: Opportunities and Challenges
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
A comparison of the RTU hardware RTOS with a hardware/software RTOS
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
The ArchC architecture description language and tools
International Journal of Parallel Programming
Nomadik®: AMobile Multimedia Application Processor Platform
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Light speed labeling: efficient connected component labeling on RISC architectures
Journal of Real-Time Image Processing
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
FlexTiles: a globally homogeneous but locally heterogeneous manycore architecture
Proceedings of the 6th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
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Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. Within this framework, this paper presents an architecture, named SCMP. This asymmetric multiprocessor can support dynamic migration and preemption of tasks, thanks to a concurrent control of tasks, while offering a specific data sharing solution. Its tasks are controlled by a dedicated HW-RTOS that allows online scheduling of independent real-time and non-real-time tasks. By incorporating a connected component labeling algorithm into this platform, we have been able to measure its benefits for real-time and dynamic image processing.