Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study

Authors:
Bingfeng Mei;Serge Vernalde;Diederik Verkest;Rudy Lauwereins
Affiliations:
-;-;-;-
Venue:
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Year:
2004

Citing 7
Cited 56

Effective compiler support for predicated execution using the hyperblock

MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems

MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
REMARC (abstract): reconfigurable multimedia array coprocessor

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications

IEEE Transactions on Computers
RaPiD - Reconfigurable Pipelined Datapath

FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
CommBench-a telecommunications benchmark for network processors

ISPASS '00 Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software

Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture

IEEE Transactions on Computers
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Designing real-time H.264 decoders with dataflow architectures

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture

Proceedings of the 2006 international symposium on Low power electronics and design
Compiler assisted architectural exploration for coarse grained reconfigurable arrays

Proceedings of the 17th ACM Great Lakes symposium on VLSI
Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture

The Journal of Supercomputing
A unified evaluation framework for coarse grained reconfigurable array architectures

Proceedings of the 4th international conference on Computing frontiers
Speedups in embedded systems with a high-performance coprocessor datapath

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor

Proceedings of the conference on Design, automation and test in Europe
An overview of reconfigurable hardware in embedded systems

EURASIP Journal on Embedded Systems
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH

ACM Transactions on Embedded Computing Systems (TECS)
Design space exploration for a coarse grain accelerator

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Speedups from extending embedded processors with a high-performance coarse-grained reconfigurable data-path

Journal of Systems Architecture: the EUROMICRO Journal
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors

ACM Transactions on Embedded Computing Systems (TECS)
An architecture framework for an adaptive extensible processor

The Journal of Supercomputing
Optimizing near-ML MIMO detector for SDR baseband on parallel programmable architectures

Proceedings of the conference on Design, automation and test in Europe
Generic multi-phase software-pipelined Partial-FFT on instruction-level-parallel architectures and SDR baseband applications

Proceedings of the conference on Design, automation and test in Europe
High-level modelling and exploration of coarse-grained re-configurable architectures

Proceedings of the conference on Design, automation and test in Europe
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator

ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems

ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
A back-end compiler with fast compilation for VLIW based dynamic reconfigurable processor

WSEAS Transactions on Computers
Coordinated concurrent memory accesses on a reconfigurable multimedia accelerator

Microprocessors & Microsystems
Resource management and task partitioning and scheduling on a run-time reconfigurable embedded system

Computers and Electrical Engineering
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
An adaptive compiler method for scheduling and place-and-route for VLIW-based dynamic reconfigurable processor

ICCOMP'08 Proceedings of the 12th WSEAS international conference on Computers
Resource aware mapping on coarse grained reconfigurable arrays

Microprocessors & Microsystems
A design flow for architecture exploration and implementation of partially reconfigurable processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs

IEICE - Transactions on Information and Systems
Dynamic context management for low power coarse-grained reconfigurable architecture

Proceedings of the 19th ACM Great Lakes symposium on VLSI
Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor

Microprocessors & Microsystems
An efficient partitioning and scheduling algorithm for streaming applications on FPGA with resource constraint

PDCS '07 Proceedings of the 19th IASTED International Conference on Parallel and Distributed Computing and Systems
Generic multiphase software pipelined partial FFT on instruction level parallel architectures

IEEE Transactions on Signal Processing
CGADL: an architecture description language for coarse-grained reconfigurable arrays

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors

Journal of Signal Processing Systems
SCMP architecture: an asymmetric multiprocessor system-on-chip for dynamic applications

Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A low-power DSP for wireless communications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design space exploration for efficient resource utilization in coarse-grained reconfigurable architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A graph drawing based spatial mapping algorithm for coarse-grained reconfigurable architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power reconfiguration technique for coarse-grained reconfigurable architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An instruction-scheduling-aware data partitioning technique for coarse-grained reconfigurable architectures

Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Exploiting the distributed foreground memory in coarse grain reconfigurable arrays for reducing the memory bottleneck in DSP applications

SSIP'05 Proceedings of the 5th WSEAS international conference on Signal, speech and image processing
Performance improvements of microprocessor platforms with a coarse-grained reconfigurable data-path

ICS'06 Proceedings of the 10th WSEAS international conference on Systems
Memory-Aware application mapping on coarse-grained reconfigurable arrays

HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
Improving performance and energy efficiency of embedded processors via post-fabrication instruction set customization

The Journal of Supercomputing
EPIMap: using epimorphism to map applications on CGRAs

Proceedings of the 49th Annual Design Automation Conference
A coarse-grained reconfigurable architecture with compilation for high performance

International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA

ACM Transactions on Architecture and Code Optimization (TACO)
DRMA: dynamically reconfigurable MPSoC architecture

Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Ingredients of adaptability: a survey of reconfigurable processors

VLSI Design
Configurable range memory for effective data reuse on programmable accelerators

ACM Transactions on Design Automation of Electronic Systems (TODAES)
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms

Journal of Real-Time Image Processing

Quantified Score

Hi-index	0.01

Visualization

Abstract

Coarse-grained reconfigurable architectures have seen growing importance recently. Design tools and methodology are essential to their success. Based on our previous work on modulo scheduling algorithms and a novel architecture with tightly coupled VLIW/reconfigurable matrix, we present a C-based design flow using an MPEG-2 decoder as a design example. The application is mapped to the architecture in less than one person-week starting from a software implementation. The kernel and overall speedup over the reference VLIW are 4.84 and 3.05 respectively. The case study shows that our methodology and architecture can deliver a competitive package in terms of design efforts and performance over other programmable architectures.