Very Long Instruction Word architectures and the ELI-512
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements
IEEE Transactions on Computers
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Vector-µSIMD-VLIW Architecture for Multimedia Applications
ICPP '05 Proceedings of the 2005 International Conference on Parallel Processing
Design methodology for pipelined heterogeneous multiprocessor system
Proceedings of the 44th annual Design Automation Conference
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Composable Lightweight Processors
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
MPLEM: An 80-processor FPGA Based Multiprocessor System
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
Overview of FPGA-Based Multiprocessor Systems
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
Architecture enhancements for the ADRES coarse-grained reconfigurable array
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Shared reconfigurable fabric for multi-core customization
Proceedings of the 48th Design Automation Conference
Bahurupi: A polymorphic heterogeneous multi-core architecture
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Application-specific heterogeneous multiprocessor synthesis using extensible processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EGRA: A Coarse Grained Reconfigurable Architectural Template
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proposing of Developed Advance Encryption Standard
DESE '11 Proceedings of the 2011 Developments in E-systems Engineering
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Embedded systems are ubiquitous and are deployed in a large range of applications. Designing and fabricating Integrated Circuits (ICs) targeting such different range of applications is expensive. Designers seek flexible processors which efficiently execute a multitude of applications. FPGAs are considered affordable, but design cost, high reconfiguration delay and power consumption are all prohibitive. In this paper, we propose a novel ASIC based flexible MPSoC architecture, which can execute separate tasks in parallel, and it can be configured to execute single task with wide data widths or execute multiple tasks with varying data widths. The architecture presented, called Dynamically Reconfigurable MPSoC Architecture (DRMA), can be rapidly reconfigured through instructions. We present applications as case studies to showcase the flexibility and efficacy of DRMA. Results show for an additional area overhead of about 5%, the system is capable of working as four 32-bit processors, a single 128 bit processor or as a pipelined processing system.