Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications

Authors:
John Oliver;Ravishankar Rao;Diana Franklin;Frederic T. Chong;Venkatesh Akella
Affiliations:
(Correspd. 2064 Kemper Hall, Davis, CA 95616-5294, USA. Tel.: +1 530 752 1417) University of California, Davis, USA;University of California, Davis, USA;California Polytechnic State University, San Luis Obispo, USA;University of California, Santa Barbara, USA;University of California, Davis, USA
Venue:
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
Year:
2006

Citing 7
Cited 3

A bandwidth-efficient architecture for media processing

MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Software Synthesis from Dataflow Graphs

Software Synthesis from Dataflow Graphs
Synthesis of Embedded Software from Synchronous Dataflow Specifications

Journal of VLSI Signal Processing Systems
Datapath design for a VLIW Video Signal Processor

HPCA '97 Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture
A low-cost and low-power multi-standard video encoder

Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor

Proceedings of the 31st annual international symposium on Computer architecture
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams

Proceedings of the 31st annual international symposium on Computer architecture

Decentralized evolutionary optimization approach to the p-median problem

Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures

ACM Transactions on Embedded Computing Systems (TECS)
DRMA: dynamically reconfigurable MPSoC architecture

Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present an overview of the Synchroscalar single-chip, multi-core processor. Through the design of Synchroscalar, we find that high energy efficiency and low complexity can be attained through parallelization. The importance of adequate inter-core interconnect is also demonstrated. We discuss the impact of having multiple frequency and voltage domains on chip to reduce the power consumption where parallelization fails. Finally, we investigate how the ad-hoc selection of tile size that is currently used in most single-chip multi-core processors impacts the power consumption of these architectures.