A low-cost and low-power multi-standard video encoder

Authors:
R. Peset Llopis;R. Sethuraman;C. Alba Pinto;H. Peters;S. Maul;M. Oosterhuis
Affiliations:
Philips Research Laboratories, Eindhoven, The Netherlands;Philips Research Laboratories, Eindhoven, The Netherlands;Philips Research Laboratories, Eindhoven, The Netherlands;Philips Research Laboratories, Eindhoven, The Netherlands;Philips Research Laboratories, Eindhoven, The Netherlands;Philips Research Laboratories, Eindhoven, The Netherlands
Venue:
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Year:
2003

Citing 2
Cited 3

DCT-Domain Embedded Memory Compression for Hybrid Video Coders

Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
Image and Video Compression Standards: Algorithms and Architectures

Image and Video Compression Standards: Algorithms and Architectures

Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor

Proceedings of the 31st annual international symposium on Computer architecture
Low-cost super-resolution algorithms implementation over a HW/SW video compression platform

EURASIP Journal on Applied Signal Processing
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications

Journal of Embedded Computing - Issues in embedded single-chip multicore architectures

Quantified Score

Hi-index	0.00

Visualization

Abstract

Video encoders are an important IP block in mobile multimedia systems. In this paper, we describe a low-cost low-power multi-standard (MPEG4, JPEG, and H.263) video/image encoder. The low-cost and low-power aspects are achieved by the right choice of algorithms and architectures. In the algorithm front, an embedded compression technique for reducing the size of loop memory has enabled a single-chip low-cost realization of the encoder. In the architectural front, an efficient hardware-software partitioning has contributed to the design of a low-power encoder. Further, the hardware components that accelerate the kernels of encoding are implemented as application specific instruction-set processors (ASIPs) thereby providing flexibility to address multi-standard encoding. The power and area estimates for the encoder for QCIF@15fps in 0.18um CMOS technology are 30mW and 20mm2 respectively including the loop memory.