A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor

Authors:
Farhad Mehdipour;Hamid Noori;Bahman Javadi;Hiroaki Honda;Koji Inoue;Kazuaki Murakami
Affiliations:
Kyushu University, Japan;Institute of Systems, Information Technologies and Nanotechnologies, Japan;Amirkabir University of Technology, Iran;Institute of Systems, Information Technologies and Nanotechnologies, Japan;Kyushu University, Japan;Kyushu University, Japan
Venue:
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Year:
2009

Citing 7
Cited 0

Computer system design using a hierarchical approach to performance evaluation

Communications of the ACM
Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation

Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Reconfigurable Instruction Set Processors from a Hardware/Software Perspective

IEEE Transactions on Software Engineering
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study

Proceedings of the conference on Design, automation and test in Europe - Volume 2
Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization

Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Exploring the design space of LUT-based transparent accelerators

Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Design space exploration for a coarse grain accelerator

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO*) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.