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PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
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ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
IEEE Transactions on Computers
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IEEE Transactions on Circuits and Systems for Video Technology
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This paper introduces the mapping of MPEG video decoders on ADRES, IMEC's new coarse-grain reconfigurable and fully C-programmable array processor that targets nomadic devices. ADRES is a flexible template that allows the instantiation of many different processor versions. An XML-based architecture description language allows a designer to easily generate different processor instances with full compiler support by specifying different values for the communication topology, the number and size of local register files and functional units and supported instruction set. ADRES supports a VLIW-like programming model with a pure VLIW mode for legacy code, and a (coarse-grain reconfigurable) array mode with very high parallelism for the processing of compute intensive loops. We demonstrate the mapping of two video decoders MPEG-2 and AVC, and discuss the performance trade-offs for two critical kernels: IDCT and integer transform. As a result, an ADRES based system can perform AVC decoding in CIF resolution with less then 50MHz on a 4x4 array processor.