Scalable Processor Instruction Set Extension

Authors:
Jurgen Becker;Alexander Thomas
Affiliations:
University of Karlsruhe;University of Karlsruhe
Venue:
IEEE Design & Test
Year:
2005

Citing 6
Cited 9

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On SPARC LEON-2 ISA extensions experiments for MPEG encoding acceleration

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On SPARC LEON-2 ISA extensions experiments for MPEG encoding acceleration

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Speedups from extending embedded processors with a high-performance coarse-grained reconfigurable data-path

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Speedups and energy reductions from mapping DSP applications on an embedded reconfigurable system

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Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor

Microprocessors & Microsystems
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware

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Performance improvements of microprocessor platforms with a coarse-grained reconfigurable data-path

ICS'06 Proceedings of the 10th WSEAS international conference on Systems

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Abstract

Editor's note: Coarse-grained reconfigurable platforms are good for parallel data-intensive applications but inefficient for sequential control-dominated code. This article (selected from the best of the SBCCI 2003 papers) explores the integration of the general-purpose, Sparc-compliant Leon processor with the Extreme Processing Platform reconfigurable data path. The integration's goal is to optimize the execution of complex multimedia applications such as MPEG-4.--Fadi J. Kurdahi, University of California, Irvine