Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC)

Authors:
Jürgen Becker;Martin Vorbach
Affiliations:
-;-
Venue:
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Year:
2003

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Abstract

This paper describes the actual status and results of a dynamically Configurable System-on-Chip (CSoC) integration, consisting of a SPARC-compatible LEON processor-core, a commercial coarse-grain XPP-array of suitable sizefrom PACT XPP Technologies AG, and application-tailoredglobal/local memory topology with efficient Amba-basedcommunication interfaces. The given adaptive architectureis synthesized within an industrial/academic SoC projectonto 0.18 and 0.13 mm UMC CMOS technologies at Universitaet Karlsruhe (TH). Due to exponential increasing CMOSmask costs, essential aspects for the industry are now adaptivity of SoCs, which can be realized by integrating reconfigurable re-usable hardware parts on differentgranularities into Configurable Systems-on-Chip (CSoCs).