Discrete-time signal processing
Discrete-time signal processing
Reconfigurable computing: what, why, and implications for design automation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IEEE Transactions on Computers
Re-configurable computing in wireless
Proceedings of the 38th annual Design Automation Conference
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System
Journal of VLSI Signal Processing Systems
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Design Methodology of a Configurable System-on-Chip Architecture
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
On design and implementation of a decimation filter for multistandard wireless transceivers
IEEE Transactions on Wireless Communications
Next-generation wireless communications concepts and technologies
IEEE Communications Magazine
A reconfigurable 8 GOP ASIC architecture for high-speed data communications
IEEE Journal on Selected Areas in Communications
Integration, the VLSI Journal
A reconfigurable systolic array architecture for multicarrier wireless and multirate applications
International Journal of Reconfigurable Computing
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
A bumpless switching scheme for dynamic reconfiguration
CDVE'07 Proceedings of the 4th international conference on Cooperative design, visualization, and engineering
Design of priority-based active queue management for a high-performance IP switch
Computers and Electrical Engineering
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This paper presents a Configurable System-on-Chip (CSoC) architecture that includes programmable and reconfigurable hardware to cope with the flexibility and real-time signal processing demands in future telecommunication and multimedia systems. A programmable micro Task Controller (mTC) with a small instruction set and a novel pipelined configuration technique with descriptors as configuration templates allows a dynamic use of physical processing resources. The CSoC architecture provides a micro-task based programming model, approves a library-based design approach to reduce developing time and costs and allows forward compatibility to other architecture families. It is shown to be easy scalable to future VLSI technologies where over a hundred processing cells on a single chip will be feasible to deal with the inherent dynamics of future applications and system requirements. Several mappings of commonly used signal processing algorithms and implementation results are given for a standard cell ASIC design realization in 0.18 µm 6-layer UMC CMOS technology.