Managing pipeline-reconfigurable FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Partitioning sequential circuits on dynamically reconfiguable FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
HSRA: high-speed, hierarchical synchronous reconfigurable array
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Memory interfacing and instruction specification for reconfigurable processors
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
String matching on multicontext FPGAs using self-reconfiguration
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs
IEEE Transactions on Computers
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Temporal logic replication for dynamically reconfigurable FPGA partitioning
Proceedings of the 2002 international symposium on Physical design
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
A fast, inexpensive and scalable hardware acceleration technique for functional simulation
Proceedings of the 39th annual Design Automation Conference
The first real operating system for reconfigurable computers
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
The management of applications for reconfigurable computing using an operating system
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
A SAT Solver Using Reconfigurable Hardware and Virtual Logic
Journal of Automated Reasoning
Configuration relocation and defragmentation for run-time reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance-driven placement for dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A pipelined configurable gate array for embedded processors
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
A Self-Reconfigurable Gate Array Architecture
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Behavioural Language Compilation with Virtual Hardware Management
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
It's FPL, Jim - But Not as We Know It! Opportunities for the New Commercial Architectures
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Configuration Caching and Swapping
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Run-Time Optimized Reconfiguration Using Instruction Forecasting
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Run-Time Adaptive Flexible Instruction Processors
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A reconfigurable functional unit for TriMedia/CPU64. A case study
Embedded processor design challenges
Dynamic Precision Management for Loop Computations on Reconfigurable Architectures
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Configuration Caching Management Techniques for Reconfigurable Computing
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Context Switching in a Run-Time Reconfigurable System
The Journal of Supercomputing
The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Temporal floorplanning using 3D-subTCG
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Pel reconstruction on FPGA-augmented TriMedia
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
Integration, the VLSI Journal
Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Proceedings of the 43rd annual Design Automation Conference
Efficient hardware checkpointing: concepts, overhead analysis, and implementation
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Microprocessors & Microsystems
Automatic Design of Area-Efficient Configurable ASIC Cores
IEEE Transactions on Computers
Proceedings of the 44th annual Design Automation Conference
Modeling and design of fault-tolerant and self-adaptive reconfigurable networked embedded systems
EURASIP Journal on Embedded Systems
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
A Network of Time-Division Multiplexed Wiring for FPGAs
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Fast Optical Reconfiguration of a Nine-Context DORGA
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
A nine-context programmable optically reconfigurable gate array with semiconductor lasers
Proceedings of the 19th ACM Great Lakes symposium on VLSI
An inversion/non-inversion dynamic optically reconfigurable gate array VLSI
WSEAS Transactions on Circuits and Systems
Scaling prospect of optically differential reconfigurable gate array VLSIs
Analog Integrated Circuits and Signal Processing
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Inversion/non-inversion dynamic optically reconfigurable gate array
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
A hybrid nano/CMOS dynamically reconfigurable system—Part I: Architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Dynamic reconfiguration architectures for multi-context FPGAs
Computers and Electrical Engineering
A minimum communication cost algorithm for dynamically reconfigurable computing system
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
An improved architecture for optimizing partitioning cost of time-multiplexed FPGA
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
A parallel partitioning algorithm for parallel reconfigurable computing
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Power consumption advantage of a dynamic optically reconfigurable gate array
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
2D defragmentation heuristics for hardware multitasking on reconfigurable devices
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A cost-effective context memory structure for dynamically reconfigurable processors
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
System-level power-performance tradeoffs for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Scientific Application Demands on a Reconfigurable Functional Unit Interface
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A dynamic reconfigurable CPLD architecture for structured ASIC technology
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Design and analysis of adaptive processor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A configuration system architecture supporting bit-stream compression for FPGAs
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Power minimization for dynamically reconfigurable FPGA partitioning
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Location, location, location: the role of spatial locality in asymptotic energy minimization
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
SRAM-based NATURE: a dynamically reconfigurable FPGA based on 10T low-power SRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes the architecture of a time-multiplexed FPGA. Eight configurations of the FPGA are stored in on-chip memory. This inactive on-chip memory is distributed around the chip, and accessible so that the entire configuration of the FPGA can be changed in a single cycle of the memory. The entire configuration of the FPGA can be loaded from this on-chip memory in 30 ns. Inactive memory is accessible as block RAM for applications. The FPGA is based on the Xilinx XC4000E FPGA, and includes extensions for dealing with state saving and forwarding and for increased routing demand due to time-multiplexing the hardware.