Introduction to algorithms
Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Partitioning using second-order information and stochastic-gain functions
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Partitioning sequential circuits on dynamically reconfiguable FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Network flow based circuit partitioning for time-multiplexed FPGAs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Performance-Oriented Fully Routable Dynamic Architecture for a Field
Performance-Oriented Fully Routable Dynamic Architecture for a Field
Temporal logic replication for dynamically reconfigurable FPGA partitioning
Proceedings of the 2002 international symposium on Physical design
Performance-driven placement for dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
A minimum communication cost algorithm for dynamically reconfigurable computing system
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Power minimization for dynamically reconfigurable FPGA partitioning
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
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Improving logic density by time-sharing, time-multiplexed FPGAs (TMFPGAs) have become an important research topic for reconfigurable computing. Due to the precedence and capacity constraints in TMFPGAs, the clustering and partitioning problems for TMFPGAs are different from the traditional ones. In this paper, we propose a two-phase hierarchical approach to solve the partitioning problem for TMFPGAs. With the precedence and capacity considerations for both phases, the first phase clusters nodes to reduce the problem size, and the second phase applies a probability-based iterative-improvement approach to minimize cut cost. Experimental results based on the Xilinx TMFPGA architecture show that our algorithm significantly outperforms previous works.