Temporal logic replication for dynamically reconfigurable FPGA partitioning

  • Authors:
  • Wai-Kei Mak;Evangeline F. Y. Young

  • Affiliations:
  • University of South Florida, Tampa, FL;The Chinese University of Hong Kong, Shatin, N.T., Hong Kong

  • Venue:
  • Proceedings of the 2002 international symposium on Physical design
  • Year:
  • 2002

Quantified Score

Hi-index 0.00

Visualization

Abstract

In this paper, we propose the idea of temporal logic replication in dynamically reconfigurable field-programmable gate array partitioning to reduce communication cost. Temporal logic replication has never been explored before. We define the min-area min-cut replication problem given a k-stage temporal partition satisfying all temporal constraints and devise an optimal algorithm to solve this problem. We have also devised a flow-based replication heuristic in case there is a tight area bound that limits the amount of replication. In addition, we will present a correct network flow model for partitioning sequential circuits temporally.