High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Performance-Oriented Fully Routable Dynamic Architecture for a Field
Performance-Oriented Fully Routable Dynamic Architecture for a Field
Network flow based circuit partitioning for time-multiplexed FPGAs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Circuit partitioning for dynamically reconfigurable FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs
IEEE Transactions on Computers
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
A memory coherence technique for online transient error recovery of FPGA configurations
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Temporal logic replication for dynamically reconfigurable FPGA partitioning
Proceedings of the 2002 international symposium on Physical design
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
A fast, inexpensive and scalable hardware acceleration technique for functional simulation
Proceedings of the 39th annual Design Automation Conference
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
Performance-driven placement for dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Implementation of Virtual Circuits by Means of the FIPSOC Devices
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
A General Hardware Design Model for Multicontext FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
An optimal algorithm for minimizing run-time reconfiguration delay
ACM Transactions on Embedded Computing Systems (TECS)
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
Modeling and optimizing run-time reconfiguration using evolutionary computation
ACM Transactions on Embedded Computing Systems (TECS)
Temporal partitioning data flow graphs for dynamically reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Transmuting coprocessors: dynamic loading of FPGA coprocessors
Proceedings of the 46th Annual Design Automation Conference
An improved architecture for optimizing partitioning cost of time-multiplexed FPGA
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
High-level synthesis with reconfigurable datapath components
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Combining temporal partitioning and temporal placement techniques for communication cost improvement
Advances in Engineering Software
Power minimization for dynamically reconfigurable FPGA partitioning
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Temporal partitioning of data flow graphs for reconfigurable architectures
International Journal of Computational Science and Engineering
Meta-algorithms for scheduling a chain of coarse-grained tasks on an array of reconfigurable FPGAs
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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An algorithm is presented for partitioning a design in time. The algorithm devides a large, technology-mapped design into multiple configurations of a time-multiplexed FPGA. These configurations are rapidly executed in the FPGA to emulate the large design. The tool includes facilities for optimizing the partitioning to improve routability, for fitting the design into more configurations than the depth of the critical path and for compressing the critical path of the design into fewer configurations, both to fit the design into the device and to improve performance. Scheduling results are shown for mapping designs into an 8-configuration time-multiplexed FPGA and for architecture investigation for a time-multiplexed FPGA.