VLSI array processors
The JPEG still picture compression standard
Communications of the ACM - Special issue on digital multimedia systems
Optimal VLSI architectural synthesis: area, performance and testability
Optimal VLSI architectural synthesis: area, performance and testability
Optimal synthesis of multichip architectures
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
High-level synthesis with pin constraints for multiple-chip designs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Spectral-based multi-way FPGA partitioning
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multiple FPGA partitioning with performance optimization
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Sequencing run-time reconfigured hardware with software
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Optimal temporal partitioning and synthesis for reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
Layout-driven high level synthesis for FPGA based architectures
Proceedings of the conference on Design, automation and test in Europe
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
High Performance Compilers for Parallel Computing
High Performance Compilers for Parallel Computing
Implementation Approaches for Reconfigurable Logic Applications
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Architectural Synthesis Techniques for Dynamically Reconfigurable Logic
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Hardware/Software Partitioning using Integer Programming
EDTC '96 Proceedings of the 1996 European conference on Design and Test
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A Run-Time Reconfigurable Engine for Image Interpolation
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Temporal Partitioning and Scheduling for Reconfigurable Computing
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Object Oriented Circuit-Generators in Java
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The Design and Implementation of a Context Switching FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Automating Production of Run-Time Reconfigurable Designs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A Prototyping System for High Performance Communication Systems
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
System-level codesign of mixed hardware-software systems
System-level codesign of mixed hardware-software systems
Logic emulation with virtual wires
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Force-Directed Scheduling based architecture generation algorithm and design tool for FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
Evaluation of runtime task mapping using the rSesame framework
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
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The reconfiguration capability of modern FPGA devices can beutilized to execute an application by partitioning it into multiplesegments such that each segment is executed one after the other onthe device. This division of an application into multiplereconfigurable segments is called temporal partitioning. Wepresent an automated temporal partitioning technique for acyclicbehavior level task graphs. To be effective, any behavior-levelpartitioning method should ensure that each temporal partition meetsthe underlying resource constraints. For this, a knowledge of theimplementation cost of each task on the hardware should be known.Since multiple implementations of a task that differ in area anddelay are possible, we perform design-space exploration tochoose the best implementation of a task from among the availableimplementations.To overcome the high reconfiguration overheadof the current day FPGA devices, we propose integration of thetemporal partitioning and design space exploration methodology withblock-processing. Block-processing is used to processmultiple blocks of data on each temporal partition so as to amortizethe reconfiguration time. We focus on applications that can berepresented as task graphs that have to be executed many times over alarge set of input data. We have integrated block-processing in thetemporal partitioning framework so that it also influences the designpoint selection for each task. However, this does not exclude usageof our system for designs for which block-processing is not possible.For both block-processing and non block-processing designs ouralgorithm selects the best possible design point to minimize theexecution time of the design.We present an ILP-basedmethodology for the integrated temporal partitioning, design spaceexploration and block-processing technique that is solved tooptimality for small sized design problems and in an iterativeconstraint satisfaction approach for large sized design problems. Wedemonstrate with extensive experimental results for the DiscreteCosine Transform (DCT) and random graphs the validity of ourapproach.