Partitioning sparse matrices with eigenvectors of graphs
SIAM Journal on Matrix Analysis and Applications
An efficient method of partitioning circuits for multiple-FPGA implementation.
DAC '93 Proceedings of the 30th international Design Automation Conference
Cost minimization of partitions into multiple devices
DAC '93 Proceedings of the 30th international Design Automation Conference
On routability prediction for field-programmable gate arrays
DAC '93 Proceedings of the 30th international Design Automation Conference
Circuit partitioning for huge logic emulation systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
Multi-way partitioning via spacefilling curves and dynamic programming
DAC '94 Proceedings of the 31st annual Design Automation Conference
Routable Technologie Mapping for LUT FPGAs
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Placement-Based Partitioning for Lookup-Table-Based FPGAs
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Network flow based multi-way partitioning with area and pin constraints
Proceedings of the 1997 international symposium on Physical design
Circuit partitioning with complex resource constraints in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Multiway FPGA partitioning by fully exploiting design hierarchy
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
A high-level clustering algorithm targeting dual Vdd FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Recent research on FPGA partitioning has focussed on finding minimum cuts between partitions without regard to the routability of the partitioned subcircuits. In this paper we develop a spectral approach to multi-way partitioning in which the primary goal is to produce routable subcircuits while maximizing FPGA device utilization. To assist the partitioner in assessing the routability of the partitioned subcircuits, we have developed a theory to predict the routability of the partitioned subcircuits prior to partitioning. Advancement over the current work is evidenced by results of experiments on the standard MCNC benchmarks.