Cost minimization of partitions into multiple devices

Multi-way netlist partitioning into heterogeneous FPGAs and minimization of total device cost and interconnect

DAC '94 Proceedings of the 31st annual Design Automation Conference

Circuit partitioning for huge logic emulation systems

DAC '94 Proceedings of the 31st annual Design Automation Conference

Performance-driven simultaneous place and route for row-based FPGAs

DAC '94 Proceedings of the 31st annual Design Automation Conference

A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions

EURO-DAC '94 Proceedings of the conference on European design automation

Spectral-based multi-way FPGA partitioning

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

Multi-way system partitioning into a single type or multiple types of FPGAs

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

Multi-way partitioning for minimum delay for look-up table based FPGAs

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Device selection for system partitioning

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation

Multiway netlist partitioning onto FPGA-based board architecture

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation

PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Multi-way FPGA partitioning by fully exploiting design hierarchy

DAC '97 Proceedings of the 34th annual Design Automation Conference

Partitioning around roadblocks: tackling constraints with intermediate relaxations

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Network flow based multi-way partitioning with area and pin constraints

Proceedings of the 1997 international symposium on Physical design

On multilevel circuit partitioning

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Rapid Prototyping of Real-Time Information Processing Unitsfor Mechatronic Systems

Real-Time Systems

Generation of very large circuits to benchmark the partitioning of FPGA

ISPD '99 Proceedings of the 1999 international symposium on Physical design

Iterative improvement based multi-way netlist partitioning for FPGAs

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Multiway FPGA partitioning by fully exploiting design hierarchy

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Cluster-aware iterative improvement techniques for partitioning large VLSI circuits

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control

Proceedings of the 39th annual Design Automation Conference

A testability measure for hierarchical design environments

EDTC '95 Proceedings of the 1995 European conference on Design and Test

ASIC Prototyping with Reprogrammable Implementations of Large ASICs

RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)

Hierarchical Partitioning in a Rapid Prototyping Environment

RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)

A high-level clustering algorithm targeting dual Vdd FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)