An efficient method of partitioning circuits for multiple-FPGA implementation.
DAC '93 Proceedings of the 30th international Design Automation Conference
Cost minimization of partitions into multiple devices
DAC '93 Proceedings of the 30th international Design Automation Conference
A general framework for vertex orderings, with applications to netlist clustering
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DAC '94 Proceedings of the 31st annual Design Automation Conference
Circuit partitioning for huge logic emulation systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
Multi-way partitioning via spacefilling curves and dynamic programming
DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient and effective placement for very large circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Optimal replication for min-cut partitioning
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Network flow based multi-way partitioning with area and pin constraints
Proceedings of the 1997 international symposium on Physical design
Performance-driven multi-FPGA partitioning using functional clustering and replication
DAC '98 Proceedings of the 35th annual Design Automation Conference
Iterative improvement based multi-way netlist partitioning for FPGAs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Multiway FPGA partitioning by fully exploiting design hierarchy
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
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This paper considers the problem of partitioning a circuit into a collection of subcircuits, such that each subcircuit is feasible for some device from an FPGA library, and the total cost of devices is minimized. We propose a three-phase heuristic that uses ordering, clustering, and dynamic programming to achieve good solutions. Experimental comparisons are made with the previous methods of [4][9].