An efficient method of partitioning circuits for multiple-FPGA implementation.
DAC '93 Proceedings of the 30th international Design Automation Conference
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DAC '94 Proceedings of the 31st annual Design Automation Conference
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ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Performance-driven partitioning using retiming and replication
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
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IBM Journal of Research and Development
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ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a new performance-driven partitioning method for multi-FPGA designs. The proposed method consists of three steps: (1) functional-cluster formation, (2) slack computation, and (3) set-covering-based partitioning with functional replication. The proposed method performs multi-FPGA partitioning by taking into account path delays and design structural information. We introduce a functional replication technique which performs circuit replications at the functional-cluster level instead of the cell level for delay and interconnect minimization. Experimental results on a number of benchmarks and industrial designs demonstrate that the proposed method achieves high-performance and high-density multi-FPGA partitions.