Field-programmable gate arrays
Field-programmable gate arrays
On routability prediction for field-programmable gate arrays
DAC '93 Proceedings of the 30th international Design Automation Conference
On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
FPGA routing and routability estimation via Boolean satisfiability
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
A hierarchy-driven FPGA partitioning method
DAC '97 Proceedings of the 34th annual Design Automation Conference
Performance-driven multi-FPGA partitioning using functional clustering and replication
DAC '98 Proceedings of the 35th annual Design Automation Conference
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
New parallelization and convergence results for NC: a negotiation-based FPGA router
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
A Web-Based Multiuser Operating System for Reconfiguarble Computing
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
An operating system for custom computing machines based on the Xputer paradigm
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
The Trianus System and Its Application to Custom Computing
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
A Virtual Hardware Operating System for the Xilinx XC6200
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Graphs and Hypergraphs
Spectral-based multiway FPGA partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using cone structures for circuit partitioning into FPGA packages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Introducing ReConfigME: An Operating System for Reconfigurable Computing
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ReConfigME: a detailed implementation of an operating system for reconfigurable computing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Architecture and operating system support for two-dimensional runtime partial reconfiguration
The Journal of Supercomputing
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As the number of system gates available on reconfigurable platforms increase beyond 10 million, the issue of the management of these resources and their sharing among many applications and users will become more of a concern. This paper identifies the fundamental services that must be provided by an operating system for reconfigurable computing and describes a prototype implementation. The paper defines a contract between the application designer and the operating system whereby the application is defined as a task graph whose nodes are pre-placed and routed modules and whose edges define the data flow dependencies between the nodes. After loading by the operating system, the task graph node modules are grouped into partitions that occupy contiguous area on the FPGA surface. The implementation features new versions of algorithms for the allocation of area to tasks, the partitioning of an application to fit selected allocated areas and the placement and routing inside partitions. All the algorithms have small deterministic and bounded run times with near linear time complexity making them suitable to run in between time slices or at the initial loading stage of applications. Tests on the prototype with benchmark examples show that it is a feasible and that fragmentation of the area of the FPGA among many users is manageable.