Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
The management of applications for reconfigurable computing using an operating system
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
The Trianus System and Its Application to Custom Computing
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
A Virtual Hardware Operating System for the Xilinx XC6200
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Automating Production of Run-Time Reconfigurable Designs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling
ACM Transactions on Embedded Computing Systems (TECS)
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
ACM Transactions on Embedded Computing Systems (TECS)
OLLAF: a fine grained dynamically reconfigurable architecture for OS support
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
ReConfigME: a detailed implementation of an operating system for reconfigurable computing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A reconfigurable computing platform for real time embedded applications
Microprocessors & Microsystems
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ReConfigME is a complete package to manage the dynamic reconfiguration of applications running on field programmable gate arrays. ReConfigME can also be viewed as an operating system for reconfigurable computing that handles the loading of IP cores on the FPGA platform and the dynamic arrangement and rearrangement of cores on the surface of the FPGA as the execution needs of multiple applications and multiple uses sharing the same platform evolve. ReConfigME can integrate with compilers for hardware software codesigned applications. We describe all the major components that make up the operating system and give preliminary results from the first prototype. These indicate that ReConfigME is a feasible basis for software like development of reconfigurable applications.