Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Configurable hardware: a new paradigm for computation
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Empirical evaluation of some high-level synthesis scheduling heuristics
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
DPGA utilization and application
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Programmable active memories: reconfigurable systems come of age
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer organization and architecture (4th ed.): designing for performance
Computer organization and architecture (4th ed.): designing for performance
Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Computer Architecture: Pipelined and Parallel Processor Design
Computer Architecture: Pipelined and Parallel Processor Design
Partitioning and Scheduling Parallel Programs for Multiprocessors
Partitioning and Scheduling Parallel Programs for Multiprocessors
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
FPGA and CPLD Architectures: A Tutorial
IEEE Design & Test
REACT: Reactive Environment for Runtime Reconfiguration
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
RACE: Reconfigurable and Adaptive Computing Environment
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
The Trianus System and Its Application to Custom Computing
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Asynchronous 2-D discrete cosine transform core processor
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Emulating Large Designs on Small Reconfigurable Hardware
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
Novel Techniques for High Performance Field
Novel Techniques for High Performance Field
Performance-Oriented Fully Routable Dynamic Architecture for a Field
Performance-Oriented Fully Routable Dynamic Architecture for a Field
Logic emulation with virtual wires
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
A Framework for Run-time Reconfigurable Systems
The Journal of Supercomputing
The management of applications for reconfigurable computing using an operating system
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
Reconfigurable media processing
Parallel Computing - Parallel computing in image and video processing
An evolutionary approach to dynamic task scheduling on FPGAs with restricted buffer
Journal of Parallel and Distributed Computing - Problems in parallel and distributed computing: Solutions based on evolutionary paradigms
Loop Pipelining and Optimization for Run Time Reconfiguration
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Optimization of Run-Time Reconfigurable Embedded Systems
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Introducing ReConfigME: An Operating System for Reconfigurable Computing
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
HW/SW codesign techniques for dynamically reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model
Proceedings of the tenth international symposium on Hardware/software codesign
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Proceedings of the tenth international symposium on Hardware/software codesign
Constraints-driven scheduling and resource assignment
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling
ACM Transactions on Embedded Computing Systems (TECS)
Power-performance trade-offs for reconfigurable computing
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
Exploiting temporal idleness to reduce leakage power in programmable architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A partitioning methodology that optimises the area on reconfigurable real-time embedded systems
EURASIP Journal on Applied Signal Processing
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
An efficient framework for dynamic reconfiguration of instruction-set customization
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
An incremental temporal partitioning method for real-time reconfigurable systems
EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Temporal partitioning data flow graphs for dynamically reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
IEICE - Transactions on Information and Systems
A minimum communication cost algorithm for dynamically reconfigurable computing system
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
A parallel partitioning algorithm for parallel reconfigurable computing
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Run-time HW/SW scheduling of data flow applications on reconfigurable architectures
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Runtime reconfiguration of custom instructions for real-time embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
OveRSoC: a framework for the exploration of RTOS for RSoC platforms
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Code transformations for embedded reconfigurable computing architectures
GTTSE'09 Proceedings of the 3rd international summer school conference on Generative and transformational techniques in software engineering III
System-level power-performance tradeoffs for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Reduce SW/HW migration efforts by a RTOS in Multi-FPGA systems
CSCWD'05 Proceedings of the 9th international conference on Computer Supported Cooperative Work in Design II
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Automating resource optimisation in reconfigurable design (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Meta-algorithms for scheduling a chain of coarse-grained tasks on an array of reconfigurable FPGAs
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
Hi-index | 14.98 |
FPGA-based configurable computing machines are evolving rapidly. They offer the ability to deliver very high performance at a fraction of the cost when compared to supercomputers. The first generation of configurable computers (those with multiple FPGAs connected using a specific interconnect) used statically reconfigurable FPGAs. On these configurable computers, computations are performed by partitioning an entire task into spatially interconnected subtasks. Such configurable computers are used in logic emulation systems and for functional verification of hardware. In general, configurable computers provide the ability to reconfigure rapidly to any desired custom form. Hence, the available resources can be reused effectively to cut down the hardware costs and also improve the performance. In this paper, we introduce the concept of temporal partitioning to partition a task into temporally interconnected subtasks. Specifically, we present algorithms for temporal partitioning and scheduling data flow graphs for configurable computers. We are given a configurable computing unit (RPU) with a logic capacity of $S_{RPU}$ and a computational task represented by an acyclic data flow graph$G=(V,E)$. Computations with logic area requirements that exceed $S_{RPU}$ cannot be completely mapped on a configurable computer (using traditional spatial mapping techniques). However, a temporal partitioning of the data flow graph followed by proper scheduling can facilitate the configurable computer based execution. Temporal partitioning of the data flow graph is a $k$-way partitioning of $G=(V,E)$ such that each partitioned segment will not exceed $S_{RPU}$ in its logic requirement. Scheduling assigns an execution order to the partitioned segments so as to ensure proper execution. Thus, for each segment in $\{ s_1, s_2, \cdots, s_k \}$, scheduling assigns a unique ordering $ s_i \rightarrow j$, $1 \leq i \leq k$, $1 \leq j \leq k$, such that the computation would execute in proper sequential order as defined by the flow graph $G=(V,E)$.