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IEEE Transactions on Computers
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ACM Computing Surveys (CSUR)
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
IEEE Transactions on Computers
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Proceedings of the tenth international symposium on Hardware/software codesign
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CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
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RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
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Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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IEEE Transactions on Computers
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International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
Dynamic application model for scheduling with uncertainty on reconfigurable architectures
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
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ACM Transactions on Reconfigurable Technology and Systems (TRETS)
International Journal of Reconfigurable Computing
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This paper presents an efficient dynamic and run-time Hardware/Software scheduling approach. This scheduling heuristic consists in mapping online the different tasks of a highly dynamic application in such a way that the total execution time is minimized. We consider soft real-time data flow graph oriented applications for which the execution time is function of the input data nature. The target architecture is composed of two processors connected to a dynamically reconfigurable hardware accelerator. Our approach takes advantage of the reconfiguration property of the considered architecture to adapt the treatment to the system dynamics. We compare our heuristic with another similar approach.We present the results of our scheduling method on several image processing applications. Our experiments include simulation and synthesis results on a Virtex V-based platform. These results show a better performance against existing methods.