Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications

Authors:
Laurent Gantel;Amel Khiar;Benoit Miramond;Mohamed El Amine Benkhelifa;Lounis Kessal;Fabrice Lemonnier;Jimmy Le Rhun
Affiliations:
Thales Research and Technology France, ETIS, UMR CNRS 8051, ENSEA, University of Cergy-Pontoise;ETIS, UMR CNRS 8051, ENSEA, University of Cergy-Pontoise;ETIS, UMR CNRS 8051, ENSEA, University of Cergy-Pontoise;ETIS, UMR CNRS 8051, ENSEA, University of Cergy-Pontoise;ETIS, UMR CNRS 8051, ENSEA, University of Cergy-Pontoise;Thales Research and Technology France;Thales Research and Technology France
Venue:
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Year:
2012

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Abstract

Recent FPGAs allow the design of efficient and complex Heterogeneous Systems-on-Chip (HSoC). Namely, these systems are composed of several processors, hardware accelerators as well as communication media between all these components. Performances provided by HSoCs make them really interesting for data-flow applications, especially image processing applications. The use of this kind of architecture provides good performances but the drawback is an increase of the programming complexity. This complexity is due to the heterogeneous deployment of the application on the platform. Some functions are implemented in software to run on a processor, whereas other functions are implemented in hardware to run in a reconfigurable partition of the FPGA. This article aims to define a programming model based on the Synchronous Data-Flow model, in order to abstract the heterogeneity of the implementation and to leverage the communication issue between software and hardware actors.