A Router Architecture for Real-Time Communication in Multicomputer Networks
IEEE Transactions on Computers
Data-Driven Control Scheme for Linear Arrays: Application to a Stable Insertion Sorter
IEEE Transactions on Parallel and Distributed Systems
Providing deterministic delay guarantees in ATM networks
IEEE/ACM Transactions on Networking (TON)
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
IEEE Transactions on Computers
An FPGA-based coprocessor for real-time fieldbus traffic scheduling: architecture and implementation
Journal of Systems Architecture: the EUROMICRO Journal
FPGA based hardware scheduler for multiprocessor systems
ACC'08 Proceedings of the WSEAS International Conference on Applied Computing Conference
Hardware IP for scheduling of periodic tasks in multiprocessor systems
WSEAS Transactions on Computer Research
Run-time HW/SW scheduling of data flow applications on reconfigurable architectures
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
"Time-driven priority" flow control for real-time heterogeneous internetworking
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
A scalable and reconfigurable priority queue architecture for ATM switches
Computer Communications
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Reliable priority-based flow-control is essential for real-time applications involving hard-deadlines. However, the use of first-in-first-out (FIFO) queues in such systems introduces priority inversion resulting in unbounded transmission delays. For this reason, a priority transmission queue is critical for multimedia and mission-critical systems. Yet very few priority queue implementations exist. This paper presents the design of a novel VLSI priority packet queue (PPQ), implemented in 1.2 /spl mu/m CMOS technology. It achieves fast operation by manipulating its contents in terms of packet segments, rather than individual words. Similar to paged memory, this new segmented architecture greatly reduces implementation cost by reusing segments and avoiding storage area fragmentation. By distributing the computationally intensive priority comparison operation over the access time for an entire segment, the PPQ achieves 96% of the speed of a high-speed packet FIFO. The PPQ can either perform priority inheritance or overwrite lower priority packets to minimize the impact of queue overflow. In addition, it is suitable as a general computer network interface buffer, since it robustly handles asynchronous read and write clocks of greatly disparate frequencies. Our initial implementation achieves well over twice the speed of a nonpipelined approach with minimal additional overhead. Furthermore, scaling this design to larger capacities and more priority levels results in an even greater improvement in speed over conventional approaches.