A VLSI priority packet queue with inheritance and overwrite
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Strategic directions in real-time and embedded systems
ACM Computing Surveys (CSUR) - Special ACM 50th-anniversary issue: strategic directions in computing research
Real-Time Systems: Design Principles for Distributed Embedded Applications
Real-Time Systems: Design Principles for Distributed Embedded Applications
FASTCHART-Idea and Implementation
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
From single to multiprocessor real-time kernels in hardware
RTAS '95 Proceedings of the Real-Time Technology and Applications Symposium
Scalable hardware earliest-deadline-first scheduler for ATM switching networks
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Analysis of a Simple Model for Non-Preemptive Blocking-Free Scheduling
ECRTS '01 Proceedings of the 13th Euromicro Conference on Real-Time Systems
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Distributed computer control systems used nowadays in the industry need often to meet requirements of on-line reconfigurability so they can adjust dynamically to changes in the application environment or to evolving specifications. The communication network connecting the computer nodes, commonly a fieldbus system, must use therefore dynamic scheduling strategies, together with on-line admission control procedures that test the validity of all changes in order to guarantee the satisfaction of real-time constraints. These are both very computationally demanding tasks, something that has precluded their wide adoption. However, these algorithms also embed sufficient levels of parallelism to grant them benefits from implementations in dedicated hardware.This paper presents a scheduling coprocessor that executes dynamic real-time traffic scheduling and schedulability analysis. The FPGA-based implementation described here supports multiple scheduling policies and was tailored for the FTT-CAN protocol, but it can be used also in other fieldbuses relying on centralized scheduling. The coprocessor generates schedules in about two orders of magnitude less time than any practical network elementary cycle duration. The time to execute a schedulability test is deterministic. An evaluation based on the SAE benchmark yielded a worst-case execution time of 1.4 ms.The paper starts by discussing the scheduling problem being addressed. It describes then the coprocessor functionality and architecture, highlighting important design decisions, and its latest implementation. Finally the coprocessor performance evaluation is presented.