An FPFA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard-Time Systems
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
An FPGA-based coprocessor for real-time fieldbus traffic scheduling: architecture and implementation
Journal of Systems Architecture: the EUROMICRO Journal
FPGA based hardware scheduler for multiprocessor systems
ACC'08 Proceedings of the WSEAS International Conference on Applied Computing Conference
Hardware IP for scheduling of periodic tasks in multiprocessor systems
WSEAS Transactions on Computer Research
Run-time HW/SW scheduling of data flow applications on reconfigurable architectures
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Shared hardware data structures for hard real-time systems
Proceedings of the tenth ACM international conference on Embedded software
| Hi-index | 0.00 |
A fast, scalable hardware earliest deadline first (EDF) link scheduler for ATM switching network is developed. This EDF scheduler is a fast hardware solution suitable for real time scheduler on nodes in ATM switching networks up to 2.5 Gbps switching speed (scheduling within 0.17 /spl mu/s), capable of performing simultaneous input and output operations within two clock cycles (mostly in one clock cycle). The designed hardware is efficient since the architecture employs the minimum size EDF priority queue, combined with variable size FIFO queues for channels implemented with a two port memory buffer. Early traffic can be simply checked and delayed. Also, it is scalable with respect to the number of channels C and the total number of buffers N. Moreover, deadline folding technique eliminates the need to extend the deadline resolution. Simulation studies and layout design demonstrate the efficiency and utility of the proposed architecture.