Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
IEEE Spectrum
A VLSI priority packet queue with inheritance and overwrite
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The SP2 high-performance switch
IBM Systems Journal
Efficient network QoS provisioning based on per node traffic shaping
IEEE/ACM Transactions on Networking (TON)
Exact admission control for networks with a bounded delay service
IEEE/ACM Transactions on Networking (TON)
PP-MESS-SIM: A Flexible and Extensible Simulator for Evaluating Multicomputer Networks
IEEE Transactions on Parallel and Distributed Systems
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
IEEE Transactions on Parallel and Distributed Systems
Real-Time Communication in Multihop Networks
IEEE Transactions on Parallel and Distributed Systems
Priority Based Real-Time Communication for Large Scale Wormhole Networks
Proceedings of the 8th International Symposium on Parallel Processing
Support for Multiple Classes of Traffic in Multicomputer Routers
PCRCW '94 Proceedings of the First International Workshop on Parallel Computer Routing and Communication
Real-time communications scheduling for massively parallel processors
RTAS '95 Proceedings of the Real-Time Technology and Applications Symposium
Providing message delivery guarantees in pipelined flit-buffered multiprocessor networks
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
RTAS '97 Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97)
A simulator for real-time parallel processing architectures
SS '95 Proceedings of the 28th Annual Simulation Symposium
Hardware-efficient fair queueing architectures for high-speed networks
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 2
Providing end-to-end performance guarantees using non-work-conserving disciplines
Computer Communications
Scalable architectures for integrated traffic shaping and link scheduling in high-speed ATM switches
IEEE Journal on Selected Areas in Communications
Routing subject to quality of service constraints in integrated communication networks
IEEE Network: The Magazine of Global Internetworking
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
IEEE Transactions on Computers
Memory optimization in single chip network switch fabrics
Proceedings of the 39th annual Design Automation Conference
Guaranteeing the quality of services in networks on chip
Networks on chip
Hardware for multiconnected networks: a case study
Information Sciences—Informatics and Computer Science: An International Journal - Special issue: Informatics and computer science intelligent systems applications
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Cost considerations in network on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Computers and Electrical Engineering
Online time-constrained scheduling in linear and ring networks
Journal of Discrete Algorithms
ACM Transactions on Embedded Computing Systems (TECS)
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Parallel machines have the potential to satisfy the large computational demands of real-time applications. These applications require a predictable communication network, where time-constrained traffic requires bounds on throughput and latency, while good average performance suffices for best-effort packets. This paper presents a new router architecture that tailors low-level routing, switching, arbitration, flow-control, and deadlock-avoidance policies to the conflicting demands of each traffic class. The router implements bandwidth regulation and deadline-based scheduling, with packet switching and table-driven multicast routing, to bound end-to-end delay and buffer requirements for time-constrained traffic while allowing best-effort traffic to capitalize on the low-latency routing and switching schemes common in modern parallel machines. To limit the cost of servicing time-constrained traffic, the router includes a novel packet scheduler that shares link-scheduling logic across the multiple output ports, while masking the effects of clock rollover on the represention of packet eligibility times and deadlines. Using the Verilog hardware description language and the Epoch silicon compiler, we demonstrate that the router design meets the performance goals of both traffic classes in a single-chip solution. Verilog simulation experiments on a detailed timing model of the chip show how the implementation and performance properties of the packet scheduler scale over a range of architectural parameters.