A Router Architecture for Real-Time Communication in Multicomputer Networks
IEEE Transactions on Computers
Providing deterministic delay guarantees in ATM networks
IEEE/ACM Transactions on Networking (TON)
Timestamp snooping: an approach for extending SMPs
ACM SIGPLAN Notices
Timestamp snooping: an approach for extending SMPs
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
A binary-tree architecture for scheduling real-time systems with hard and soft tasks
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Shared hardware data structures for hard real-time systems
Proceedings of the tenth ACM international conference on Embedded software
Recursive design of hardware priority queues
Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures
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In packet-switched networks, queueing of packets at the switches can result when multiple connections share the same physical link. To accommodate a large number of connections, a switch can employ link-scheduling algorithms to prioritize the transmission of the queued packets. Due to the high-speed links and small packet sizes, a hardware solution is needed for the priority queue in order to make the link schedulers effective. But for good performance, the switch should also support a large number of pri ority levels (P) and be able to buffer a large number of packets (N). So a hardware priority queue design must be both fast and scalable (with respect to N and P) in order to be implemented effectively. In this paper, we first compare four existing hardwa re priority queue architectures, and identify scalability limitations on implementing these existing architectures for large N and P. Based on our findings, we propose two new priority queue architectures, and evaluate them using simulation results from V erilog HDL and Epoch implementations.