VLSI array processors
Performance of Synchronous and Asynchronous Schemes for VLSI Systems
IEEE Transactions on Computers
A VLSI priority packet queue with inheritance and overwrite
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A shift register architecture for high-speed data sorting
Journal of VLSI Signal Processing Systems
Introduction to Parallel Processing: Algorithms and Architectures
Introduction to Parallel Processing: Algorithms and Architectures
On Balancing Sorting on a Linear Array
IEEE Transactions on Parallel and Distributed Systems
Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Design and analysis of a systolic sorting architecture
SPDP '95 Proceedings of the 7th IEEE Symposium on Parallel and Distributeed Processing
IEEE Transactions on Computers
Arbitrary long digit integer sorter HW/SW co-design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Optimal fault-tolerant embedding of paths in twisted cubes
Journal of Parallel and Distributed Computing
Optimal Embeddings of Paths with Various Lengths in Twisted Cubes
IEEE Transactions on Parallel and Distributed Systems
Edge-pancyclicity and path-embeddability of bijective connection graphs
Information Sciences: an International Journal
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We present a strategy for designing stable insertion sorters based on linear arrays with data-driven control. The novelty of our approach lies in each data item carrying a control tag to specify how it is to be operated upon by a receiving cell and in performing two parallel comparisons within each cell. To assure first-in/first-out handling of equal key values, some data items must be marked to reflect their past histories. Such marking is conveniently carried out by modifying the data item's control tag. It is the combination of the above features that allows us to derive the first single-cycle priority queue that operates in fully pipelined mode, with no broadcasting of data values or control signals. By performing more than two parallel comparisons in each cell, the VLSI implementation cost of our stable sorter can be reduced. We show that highly cost-effective designs can be obtained by selecting an optimal cell size in terms of the number of comparators it contains.